A method for laying out an integrated circuit design based upon a netlist provided by a behavioral synthesis tool includes the steps of: (A) placing cells specified by the netlist in a layout area in a placement step, the cells including pins that are interconnected by nets; (B) verifying timing constraints...http://www.google.com/patents/US6014506?utm_source=gb-gplus-sharePatent US6014506 - Method and apparatus for improving engineering change order placement in integrated circuit designs
