The invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows and columns, each...http://www.google.com/patents/US6535431?utm_source=gb-gplus-sharePatent US6535431 - Method of adjusting program voltage in non-volatile memories, and process for fabricating a non-volatile memory device
