An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells that perform logical functions on input signals. A set of block connectors are used to provide connectability between cells and accessibility to a hierarchical...http://www.google.com/patents/US6747482?utm_source=gb-gplus-sharePatent US6747482 - Architecture and interconnect scheme for programmable logic circuits
