A double data rate (DDR) synchronous dynamic RAM (SDRAM), or DDR-SDRAM, memory controller employing a delay locked loop (DLL) circuit to delay an SDRAM data strobe (DQS) signal to the center, or ‘eye’ of the read data window. However, in distinction from conventional techniques, the initial delay...http://www.google.com/patents/US6940768?utm_source=gb-gplus-sharePatent US6940768 - Programmable data strobe offset with DLL for double data rate (DDR) RAM memory
