Excessive variation in vertical (i.e., inter-level) capacitance of multi-level metallization semiconductor devices resulting in poor RC time constants of finished devices, and over-etching of borderless vias leading to inter-level short-circuits, are simultaneously eliminated or substantially reduced...http://www.google.com/patents/US6511904?utm_source=gb-gplus-sharePatent US6511904 - Reverse mask and nitride layer deposition for reduction of vertical capacitance variation in multi-layer metallization systems
