In response to a software instruction, a static microprocessor is placed in a low current mode by disabling clock pulse generation. Means are provided for disabling a master oscillator when a STOP instruction is decoded. Additional means are provided for inhibiting clock pulses when a WAIT instruction...http://www.google.com/patents/US4758945?utm_source=gb-gplus-sharePatent US4758945 - Method for reducing power consumed by a static microprocessor
