A dynamic semiconductor memory device including memory cells divided into a plurality of blocks (1-1, 1-2). A simultaneous write enable circuit performs a write operation simultaneously upon the plurality of blocks, and a comparison circuit compares read data of one block with read data of the other...http://www.google.com/patents/US4744061?utm_source=gb-gplus-sharePatent US4744061 - Dynamic semiconductor memory device having a simultaneous test function for divided memory cell blocks
