A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked to the respective buses and further includes a plurality of queues placed within address and data paths linking the various controllers. An...http://www.google.com/patents/US6160562?utm_source=gb-gplus-sharePatent US6160562 - System and method for aligning an initial cache line of data read from local memory by an input/output device
