Disclosed is an integrated circuit that includes clock generation circuitry which generates a master clock signal and at least one other clock signal. The master clock signal and the other clock signal are transmitted through a clock distribution tree to a circuit component. In a default mode, the circuit...http://www.google.com/patents/US7162705?utm_source=gb-gplus-sharePatent US7162705 - Dynamically reconfiguring clock domains on a chip
