A MPE-FEC memory chip and method for use in a DVB-H receiver, wherein the memory chip comprises a TS demux; a RS decoder; a system bus; and a RAM unit adapted to simultaneously interface to the TS demux, the RS decoder, and the system bus through time-multiplexing, wherein the RAM unit is adapted to...http://www.google.com/patents/US7890845?utm_source=gb-gplus-sharePatent US7890845 - Integrated MPE-FEC RAM for DVB-H receivers
