An isolation region for a memory array in which the isolation region includes at least one trench region having sidewalls that extend to a bottom surface and a slit region formed beneath the final trench region, wherein the slit region is narrower than the overlying trench regions and has a void formed...http://www.google.com/patents/US20020171118?utm_source=gb-gplus-sharePatent US20020171118 - DEEP SLIT ISOLATION WITH CONTROLLED VOID
