A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections...http://www.google.com/patents/US6762076?utm_source=gb-gplus-sharePatent US6762076 - Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
