A digital PLL circuit has a data sampling circuit for sampling input data in response to N phase clocks in the direction of time. The phase of the clock corresponding to, among the sampled data, the data in which edges are evenly detected is used as a first phase or reference clock. The successive...http://www.google.com/patents/US5687203?utm_source=gb-gplus-sharePatent US5687203 - Digital phase locked loop circuit
