A method and system for reducing a latency of microprocessor instructions in transit along an instruction pipeline of a microprocessor by bypassing, at certain times, a fill buffer located between an instruction source and a trace cache unit on the instruction pipeline. The signal path through the fill...http://www.google.com/patents/US6442674?utm_source=gb-gplus-sharePatent US6442674 - Method and system for bypassing a fill buffer located along a first instruction path
