A system is disclosed for a microcontroller which permits the interruption of a sequence of instructions, each of which are executable in a fixed machine cycle in response to one of a plurality of interrupt/trap signals. The microcontroller is interrupted for one fixed period machine cycle, during which...http://www.google.com/patents/US4339796?utm_source=gb-gplus-sharePatent US4339796 - System for generating a plurality of different addresses for a working memory of a microcontroller during execution of certain instructions
