A power management system pad clock and self-test circuit includes a clock processing circuit having a input configured to receive an oscillator clock signal having a first frequency. The clock processing circuit is configured to generate a first pad clock signal having a frequency approximately equal...http://www.google.com/patents/US5983014?utm_source=gb-gplus-sharePatent US5983014 - Power management system that one of plurality of peripheral signals is selectably routed to main pad clock node during a test mode
