A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials...http://www.google.com/patents/US6784105?utm_source=gb-gplus-sharePatent US6784105 - Simultaneous native oxide removal and metal neutral deposition method
