A data signal DATA is captured by flip-flops 10 and 11 alternately every half cycle time of a clock signal CLK, outputs of the flip-flops 10 and 11 are delayed by respective delay circuits 15 and 16 to generate delayed signals 10QD and 11QD, and an output of the flip-flop 10 and the delayed signal 11QD...http://www.google.com/patents/US6944252?utm_source=gb-gplus-sharePatent US6944252 - Phase comparator circuit
