A synchronous dynamic random access memory ("SDRAM") operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located...http://www.google.com/patents/US20020016885?utm_source=gb-gplus-sharePatent US20020016885 - Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths
