An FM stereo demodulating circuit comprising a pulse counter detector 1 for generating a pulse train signal including the frequency spectrum of the FM signal, DC biasing means for current biasing the detector output about a midpoint, a subcarrier signal generator 2 and current drivers 8, 10 for generating dual polarity biased subcarrier currents, first and second transistor pairs 3, 4, the emitters of each being connected to one of the current drivers, and the bases of the pairs being cross-connected to one of the biased detector outputs, at least one reference transistor pair whose emitters are connected to a current source 11 and whose collectors are connected to each of the biased detector outputs. The currents entering the cross-connected collectors of the first and second transistor pairs, when referenced against the currents into the emitters of the reference transistor pair, produce signals proportional to the right and left channels of the FM signal.
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1. An FM stereo demodulating circuit comprising:
- a first differential transistor pair (3) further comprising a first and second transistor with their emitters connected to each other;
- a second differential transistor pair (4) further comprising a third and a fourth transistor with their emitters connected to each other;
- a third differential transistor pair (5) further comprising a fifth and a sixth transistor with their emitters connected to each other;
- a first current control means (2, 8) for controlling a first current supplied to said first differential pair for varying said first current in accordance with a positive phase signal of a sinusoidal subcarrier signal synchronized with a stereo pilot signal in a stereo composite signal which is an FM detection signal;
- a second current control means (2, 9) for controlling a second current supplied to said second differential transistor pair for varying said second current in accordance with a negative phase signal of said sinusoidal subcarrier;
- means (1, E.sub.1, R.sub.1 and R.sub.2) for generating positive and inverted phase pulse train signals having frequency spectrum components of said stereo composite signals, the respective bases of said first, fourth and fifth transistors being supplied with said positive phase pulse train signal and the respective bases of said second, third and sixth transistors being supplied with either said inverted phase pulse train signal or a predetermined bias, whereby a left and a right channel signal are obtained from the respective collector currents of at least said first to fifth transistors.
2. An FM stereo demodulating circuit, as recited in claim 1, wherein said generating means comprises a pulse counter detector and biasing means.
3. An FM stereo demodulating circuit as recited in claim 1, further comprising:
- a first current source (11) connected to the emitters of said fifth and sixth transistor;
- a second current source (12);
- a fourth differential transistor pair (6) further comprising a seventh and eighth transistor having their emitters connected to said second current source, the base of said seventh transistor being supplied with said positive phase pulse train signal and the base of said eighth transistor being supplied with said inverted phase pulse train signal; and wherein
- the collectors of said sixth and eighth transistors are connected to a given voltage;
- the collectors of said first, third and fifth transistors are connected and separated from said given voltage by a first resistor (R3), whereby the voltage on said collectors is one of said channel signals; and
- the collectors of said second, fourth and seventh transistors are connected and separated from said given voltage by a second resistor (R4), whereby the voltage on said collectors is the other of said channel signals.
4. An FM stereo demodulating circuit, as recited in claim 1, further comprising:
- a current source (11) connected to the emitters of said fifth and sixth transistor;
- a first differential amplifier circuit (14) whose inputs are respectively connected to the collectors of said fifth and sixth transistors, whereby the output of said amplifier is a main signal of said left and right channel signals; and
- a second differential amplifier circuit (16), one of whose inputs is connected to the collectors of said first and third transistors, and the other input is connected to the collectors of said second and fourth transistor, whereby the output of said amplifier is a sub-signal of said left and right channel signals.