A method for forming a CMOS device, with improved yield, performance and reliability characteristics, has been developed. Yield improvements have been addressed by the use of a dual insulator spacer, used to reduce the risk of salicide bridging, as well as the use of pocket implantation regions, used...http://www.google.com/patents/US5668024?utm_source=gb-gplus-sharePatent US5668024 - CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation process
