This invention relates to the fabrication of intergrated circuit devices and more particularly to a method for reducing the gate to drain and gate to source overlap capacitance of deep sub-micron CMOS devices, as an improved means of reducing device switching times. This is accomplished by customizing...http://www.google.com/patents/US6297106?utm_source=gb-gplus-sharePatent US6297106 - Transistors with low overlap capacitance
