A wafer-scale package structure in which a circuit board for rearranging electrode pads of a wafer is laminated on the wafer integrally. The circuit board can be divided into individual chip-size packages (CSPS) and which includes a layer of polyimide resin, and connection between the wafer and the circuit...http://www.google.com/patents/US6333469?utm_source=gb-gplus-sharePatent US6333469 - Wafer-scale package structure and circuit board attached thereto
