An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied...http://www.google.com/patents/US5321699?utm_source=gb-gplus-sharePatent US5321699 - Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels
