A non-volatile memory array includes a semiconductor substrate having a main surface, a first source/drain region and a second source/drain region. The second source/drain region is spaced apart from the first source/drain region. A well region is disposed in a portion of the semiconductor substrate...http://www.google.com/patents/US8063428?utm_source=gb-gplus-sharePatent US8063428 - Two-bits per cell not-and-gate (NAND) nitride trap memory
