An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125),...http://www.google.com/patents/US20020196059?utm_source=gb-gplus-sharePatent US20020196059 - Memory system including a memory device having a controlled output driver characteristic
