The variable latency associated with flash memory due to background data integrity operations is managed in order to allow the flash memory to be used in isochronous systems. A system processor is notified regularly of the nature and urgency of requests for time to ensure data integrity. Minimal interruptions...http://www.google.com/patents/US8099632?utm_source=gb-gplus-sharePatent US8099632 - Urgency and time window manipulation to accommodate unpredictable memory operations
