The bit streams, transporting the frames, received from lines (6) are placed in register 12 in such a way that n bits are processed in parallel during a time interval T. Parallel processor 10 counts the consecutive logical "1" bits beginning at the low order (left most) bit of the n bits received in...http://www.google.com/patents/US5119478?utm_source=gb-gplus-sharePatent US5119478 - Parallel processing method and device for receiving and transmitting HDLC SDLC bit streams
