A hazard control circuit for a cache controller that prevents overwriting of modified cache data without write back. The cache controller controls a non-blocking, N-way set associative cache that uses a write-back cache-coherency protocol. The hazard control circuit prevents data loss by deferring assignment...http://www.google.com/patents/US6286082?utm_source=gb-gplus-sharePatent US6286082 - Apparatus and method to prevent overwriting of modified cache entries prior to write back
