A computer-aided design method and apparatus for compacting semiconductor circuit layouts to meet a specified set of design rules begins by fracturing a specified circuit layout into a set of trapezoids and storing the resulting cells in a database identifying the boundaries of each cell, and...http://www.google.com/patents/US5689433?utm_source=gb-gplus-sharePatent US5689433 - Method and apparatus for compacting integrated circuits with wire length minimization 
