A multiprocessor data processing system, the processors (30) and input/output devices (32) of which share a common control unit (CCU 10) that includes a write-through cache memory (20), a memory management circuit (22) and an address translation circuit (24). The data processing system further includes...http://www.google.com/patents/US4392200?utm_source=gb-gplus-sharePatent US4392200 - Cached multiprocessor system with pipeline timing
