A semiconductor memory device uses in a test mode a clock signal from a tester to allow a test clock conversion circuit and a DLL circuit to generate a rapid internal clock. The internal clock is applied to serial parallel conversion circuits subjecting received, packetized data to serial parallel conversion,...http://www.google.com/patents/US6301190?utm_source=gb-gplus-sharePatent US6301190 - Semiconductor memory device with a rapid packet data input, capable of operation check with low speed tester
