A placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slice 100 having a plurality of basic cells 110 formed in a matrix, in which first and second power source wirings...http://www.google.com/patents/US6476425?utm_source=gb-gplus-sharePatent US6476425 - Master-slice system semiconductor integrated circuit and design method thereof
