In a data processing system a control device for an intermediate memory during a bulk data transport between two data devices. A first data device addresses a number of descriptor signals. Each descriptor signal indicates another descriptor signal, so that a sequence is formed which is cyclically coupled...http://www.google.com/patents/US4562534?utm_source=gb-gplus-sharePatent US4562534 - Data processing system having a control device for controlling an intermediate memory during a bulk data transport between a source device and a destination device
