An output multiplexing circuit for a Double Data Rate (DDR) synchronous memory device includes n first latches, n first switches, n second switches, n second latches, and two third switches. The n first latches simultaneously prefetch n-bit data transmitted from a memory cell array via a data path. The...http://www.google.com/patents/US6914829?utm_source=gb-gplus-sharePatent US6914829 - Multi-stage output multiplexing circuits and methods for double data rate synchronous memory devices
