Architecture and methods for computing with reconfigurable resistor crossbars

1. An architecture for computing, comprising:

nanometer scale crossbar switches configured to perform a logical function in response to a sequence of pulses that encode logic values in the nanometer scale crossbar switches as impedances, wherein input data is latched at input latches within the nanometer scale crossbar switches and wire-AND junctions are open/closed with the result being driven out of an output latch.

2. The architecture for computing of claim 1, wherein the nanometer scale crossbar switches are configured to perform a latching function in response to the sequence of pulses.

3. The architecture for computing of claim 1, wherein the nanometer scale crossbar switches include a common type of programmable switch junction.

4. The architecture for computing of claim 3, wherein the programmable switch junctions have substantially linear impedance responses when closed.

5. The architecture for computing of claim 3, wherein the programmable switch junctions are resistive.

6. The architecture for computing of claim 1, wherein the architecture does not include diodes.

7. The architecture for computing of claim 1, wherein the architecture does not include transistors.

8. The architecture for computing of claim 1, wherein the nanometer scale crossbar switches include two wires that are crossed at a non-zero angle.

9. The architecture for computing of claim 8, wherein one or both of the two wires are made ftom a metal.

10. The architecture for computing of claim 8, wherein one of the two wires is made from a semiconductor material.

11. An architecture for computing, comprising:

a plurality of nanometer scale crossbar switches which serve as resistive circuit elements when in closed positions, the nanometer scale cross bar switches being configured to perform a logical function in response to a sequence of control inputs that encode logic values in the nanometer scale crossbar switches as impedances, wherein input data is latched at input latches within the plurality of nanometer scale crossbar switches and wire-AND junctions are open/closed with the result being driven out of an output latch.

12. The architecture for computing of claim 11, wherein the nanometer scale switches include crossbar switches.

13. The architecture for computing of claim 12, wherein the crossbar switches include two wires that are crossed at a non-zero angle.

14. The architecture for computing of claim 13, wherein one or both of the two wires are made from a metal.

15. The architecture for computing of claim 13, wherein one of the two wires is made from a semiconductor material.

16. The architecture for computing of claim 11, wherein the nanometer scale switches are configured to perform a latching function in response to the sequence of control inputs.

17. The architecture for computing of claim 11, wherein the nanometer scale switches do not include diodes.

18. The architecture for computing of claim 11, wherein the nanometer scale switches do not include transistors.

19. An architecture for computing, comprising:

arrays of nanometer scale crossbar switches that are uniform in type and that include a common type of programmable switch junctions, the arrays being configured to implement a logic function by encoding logic values in the arrays as impedances, wherein input data is latched at input latches within the arrays of nanometer scale crossbar switches and wire-AND junctions are open/closed with the result being driven out of an output latch.

20. The architecture for computing of claim 19, wherein the arrays are configured to perform a latching function.

21. The architecture for computing of claim 19, wherein the switch junctions are nanometer scale.

22. The architecture for computing of claim 19, wherein the switch junctions have substantially linear impedance responses.

23. The architecture for computing of claim 19, wherein the switch junctions are resistive.

24. The architecture for computing of claim 19, wherein the arrays do not include diodes.

25. The architecture for computing of claim 19, wherein the arrays do not include transistors.

26. The architecture for computing of claim 19, wherein the architecture is formed on a single tile type.

27. A method for computing, comprising:

providing a sequence of pulses that encodes logic values in arrays of crossbar switches as impedances such that the arrays perform logical functions, wherein input data is latched at input latches within the arrays of nanometer scale crossbar switches and wire-AND junctions are open/closed with the result being driven out of an output latch.

28. The method for computing of claim 27, wherein the arrays arc uniform in type.

29. The method for computing of claim 27, wherein the arrays include a common type of programmable switch junction.

30. The method for computing of claim 27, wherein the arrays include nanometer scale switch junctions.

31. The method for computing of claim 27, wherein the arrays do not include diodes.

32. The method for computing of claim 27, wherein the arrays do not include transistors.

33. The method for computing of claim 27, wherein the logical functions include a NAND function.

34. The method for computing of claim 27, wherein the logical functions include an exclusive OR function.

35. A method for computing comprising:

providing a sequence of pulses that allows an array of resistor crossbar switches to perform a logical function, the sequence of pulses being provided to effect a sequence of operations wherein

all junctions of the resistor crossbar switches are unconditionally opened,

input data are latched in input latches of the array,

wired-AND junctions of the array are closed,

the input latches are read, and a wired-AND function is evaluated and a result captured in an output latch of the array,

the wired-AND junctions are opened, and

the result is driven Out of the output latch.

36. A method for computing comprising:

providing a sequence of pulses that allows an array of resistor crossbar switches to perform a logical function, the sequence of pulses being provided to effect a sequence of operations wherein

all junctions of the resistor crossbar switches are unconditionally opened,

input data are latched in input latches of the array,

wired-AND junctions of the array for a first minterm are closed depending upon a corresponding first minterm bit stored in the input latches,

the input latches are read, and a wired-AND function is evaluated and a first minterm result captured in an output latch of the array,

the wired-AND junctions for the first minterm are opened,

the first minterm result is driven out of the output latch,

wired-AND junctions of the array for a second minterm are closed depending upon a corresponding second minterm bit stored in the input latches,

the input latches are read, and the wired-AND function is evaluated and a second minterm result captured in the output latch, which effectively NORs the first and second minterms together,

the wired-AND junctions for the second minterm are opened, and

a result of the first and second minterms NORed together is driven out of the output latch.