(12) United States Patent
(io) Patent No.: (45) Date of Patent:
US 7,640,398 B2 Dec. 29, 2009
(54) HIGH-SPEED INTERFACE FOR
HIGH-DENSITY FLASH WITH TWO LEVELS
OF PIPELINED CACHE
(75) Inventor: Vijay P. Adusumilli, San Jose, CA (US)
(73) Assignee: Atmel Corporation, San Jose, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 88 days.
(21) Appl.No.: 11/178,713
(22) Filed: Jul. 11, 2005
A memory circuit and a method of operating a flash or EEPROM device that has two levels of internal cache. A memory device having a memory array, sense amplifiers, a data register, cache, an input-output circuit, and a control logic circuit is configured to output data while simultaneously reading data from the memory array to the data register or simultaneously copying data from the data register to a first level of internal cache. In addition, the memory device is configured to output data while simultaneously writing data from the data register to the memory array.
20 Claims, 5 Drawing Sheets