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United States Patent [i9]
[ii] 4,125,877  Nov. 14, 1978
 DUAL PORT RANDOM ACCESS MEMORY STORAGE CELL
 Inventor: John R. Reinert, Mesa, Ariz.
 Assignee: Motorola, Inc., Schaumburg, 111.
 Appl. No.: 745,023
 Filed: Nov. 26, 1976
 Int. C1.2 G11C 7/00; Gl 1C 11/40
 U.S. CI 365/190; 307/238;
307/317 A; 365/195
 Field of Search 307/238, 289, 291, 200 A;
364/200 MS File, 900 MS File; 340/173 FF, 173 BB, 173 CC; 365/200, 190, 195, 154, 155,
 References Cited
U.S. PATENT DOCUMENTS
2,402,758 6/1946 Leverenz 340/173 CC
3,474,248 10/1969 Brown et al 340/173 CC
3,573,754 4/1971 Merryman 340/173 R
3,609,665 9/1971 Kronies 364/200
3,665,424 5/1972 Scharkowitz 340/173 R
3,676,717 7/1972 Lockwood 340/173 LI
3,914,620 10/1975 Millhollan et al 307/215
3,919,566 11/1975 Millhollan et al 340/173 FF
3,973,246 8/1976 Millhollan et al 340/173 FF
Primary Examiner—Bernard Konick
Assistant Examiner—Donald E. McElheny, Jr.
Attorney, Agent, or Firm—Anthony J. Sarli, Jr.
A dual port memory cell suitable for use in emitter coupled logic applications is accessible from two different address ports. The dual port storage cell includes first and second cross coupled cells, each including a selection conductor and a pair of diodes coupled to the cross coupled transistors to effect selection of that storage cell. The base of each of the cross coupled transistors of the first storage cell is coupled to the base of a coupling transistor, the emitter of which is connected to the base of a corresponding transistor of the other storage cell. Each dual port memory cell has two pairs of bit lines, one pair being coupled to the first storage cell and the other being coupled to the second storage cell. If one of the storage cells is selected, and the other remains unselected, the information in the selected cell is automatically written into the unselected storage cell.
15 Claims, 3 Drawing Figures
U.S. Patent Nov. 14, 1978 Sheet 1 of 2 4,125,877
U.S. Patent Nov. 14, 1978 Sheet 2 of 2 4,125,877
DUAL PORT RANDOM ACCESS MEMORY
BACKGROUND OF THE INVENTION 5
1. Field of the Invention
The invention relates to dual port random access memory storage cells which are accessible from two different address ports.
2. Brief Description Of The Prior Art 10 Briefly described, random access memory cells of
many varieties are well known in the art. However, such prior art cells are ordinarily addressable only from a single port. In other words, a binary address addressing a particular RAM cell causes a single select line or a coincidence of two select lines, such as a row select line and a column select line, to cause the addressed cell to be selected. Data is then sensed from or written into the selected storage cell on one or two bit sense lines. In 2rj many RAM cells, a single selection line causes the particular cell to be selected, and other selection circuitry activated by the same address causes the bit-sense lines to be selected. However, there are never any options for addressing and sensing and writing. The same selection 25 lines and the same bit sense lines are always utilized to access and write and sense a particular location. A particular location is always represented by a single storage element. Master slave flip-flops are well known, but these are not accessible and addressable from two sepa- 30 rate ports, and they are not bidirectional. Consequently, the storage devices of the prior art cannot be simultaneously addressed and accessed from separate sources. In certain applications especially those involving an arithmetic logic unit, this is a disadvantage. 35
SUMMARY OF THE INVENTION
An object of the invention is to provide a dual port random access memory cell which is addressable and accessible for reading and writing operations from two 40 different ports.
Another object of the invention is to provide a dual port random access memory cell wherein the contents of any particular storage cell of the dual port random access memory cell are written into all other unselected 45 storage cells of that dual port random access memory cell when that particular storage cell is selected and the others are unselected.
Briefly described, the invention is a dual port mem- 5Q ory cell which includes a first storage cell including first means for selecting the first storage cell, and also includes first and second cross coupled transistors. The dual port memory cell also includes a second storage cell including second means for selecting the second 55 storage cell and also includes third and fourth crosscoupled transistors. Coupling circuitry is provided for coupling the first storage cell to the second storage cell, such that whenever one of the two storage cells is selected and the other one is unselected, the data stored in go the selected storage cell is also written into the unselected storage cell.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic circuit diagram of a preferred 65 embodiment of the invention.
FIG. 2 is a schematic drawing representing a modification which can be made to the embodiment of FIG. 1.
FIG. 3 is a block diagram of a dual port memory circuit which employs a plurality of memory cells of the type shown in FIG. 1.
DESCRIPTION OF THE INVENTION
Referring to FIG. 1, dual port random access memory storage cell 10 includes two subcells 12 and 14, and can include additional subcells arranged in the same manner as subcells 12 and 14.
Subcell 12 includes cross-coupled transistors 16A and 19A. The base of transistor 16A is cross-coupled to the collector of transistor 19A, and the base of transistor 19A is cross-coupled to the collector of transistor 16A. The emitters of transistors 16A and 19A are connected to conductor 22A, which ordinarily would be shared with a number of other similar subcells of other dual port random access memory storage cells in the same row. Conductor 22A is connected through a current source to the negative Vee voltage. The collector of transistor 19A, which is connected to node 21A, is also connected to the bases of transistor 28A and 30A. Similarly, the collector of transistor 16A, which is connected to node 18A, is also connected to the bases of transistors 24A and 26A. Schottky diode 17A is connected between node 18A and selection conductor 15A. Selection conductor 15A would also be connected to a number of other subcells in the same row as subcell 12. Schottky diode 20A is connected between node 21A and selection conductor 15A. Resistors 29A and 23A are connected between selection conductor 15A and nodes 18A and 21A, respectively. The emitters of transistors 28A and 24A are coupled, respectively, to bitsense conductors 25A and 31A, which together form a bit-sense pair. The emitters of transistors 30A and 26A are connected, respectively, to conductors 21B and 18B, which provide coupling to the control or collector nodes of subcell 14, as explained hereinafter. The collectors of transistors 30A and 26A are connected to voltage conductor Vcc, although they could also be connected to selection conductor 15A. Connecting them to Vcc rather than selection conductor 15A provides the same operation, but reduces the capacitance of selection conductor 15A, which is a desirable result.
The construction of subcell 14 is entirely similar to the construction of subcell 12, and reference numerals are similar, except that the letter B has been used instead of the letter A to identify corresponding parts. The emitters of transistors 28B and 24B, however, are coupled to bit-sense conductors 31B and 25B, which constitute a second bit-sense pair. Subcell 14 has a separate selection conductor 15B and a separate conductor 22B, both of which are shared with other subcells in the same row, not shown. Each of the bit-sense conductors is terminated by means of a current source coupled to Vee- The emitters of transistors 30B and 26B are coupled, respectively, to nodes 21A and 18A.
As mentioned earlier, a dual port memory is one in which memory locations are accessible from two different address ports. It is desirable that the dual port capability extend both to read operations and write operations independently of each other, so that the location can be read independently from both ports, and also be written independently from both ports. Selection, sensing, and writing of cells such as the subcells 12 and 14, without the transistors 30A and 26A (or 30B and 26B) is well known in the art. For example, see U.S. Pat. No. 3,919,566, by Millhollan et al., assigned to the present assignee, and incorporated by reference herein. Also see