(19) United States
(12) Patent Application Publication (io) Pub. No.: US 2001/0053577 Al
Forbes et al. (43) Pub. Date: Dec. 20,2001
(54) METHOD OF FABRICATING A
MEMORY CELL WITH BURIED WORD AND
(76) Inventors: Leonard Forbes, Corvallis, OR (US);
Kie Y. Ahn, Chappaqua, NY (US)
SCHWEGMAN, LUNDBERG, WOESSNER &
P.O. BOX 2938
MINNEAPOLIS, MN 55402 (US)
( * ) Notice: This is a publication of a continued prosecution application (CPA) filed under 37 CFR 1.53(d).
(21) Appl. No.: 09/510,095
(22) Filed: Feb. 22, 2000
Related U.S. Application Data
(62) Division of application No. 08/889,395, filed on Jul. 8, 1997, now Pat. No. 6,191,470.
A memory cell array for a dynamic random access memory (DRAM) includes word and body lines that are buried below the active semiconductor surface in dielectric material in alternating parallel isolation trenches between adjacent ones of the memory cells. Semiconductor-on-insulator (SOI) processing techniques form the access transistor of each memory cell on a silicon island defined by the trenches and isolated from the substrate by an insulating layer. The word and body lines are oriented in the trenches to have a line width that is less than a minimum lithographic feature size F. The memory cells, including portions of the word and body lines, have a surface area of about 8 F2. Also disclosed is a process for fabricating the DRAM cell using SOI processing techniques.