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United States Patent [w]
US005828653A [ii] Patent Number: 5,828,653  Date of Patent: *Oct. 27, 1998
 QUALITY OF SERVICE PRIORITY SUBCLASSES
 Inventor: Gregory S. Goss, Lowell, Mass.
 Assignee: Cascade Communications Corp.,
[ * ] Notice: This patent issued on a continued prosecution application filed under 37 CFR 1.53(d), and is subject to the twenty year patent term provisions ol 35 U.S.C. 154(a)(2).
 Appl. No.: 639,172
 Filed: Apr. 26, 1996
 Int. C I. H04L 12/56
 U.S. CI 370/230; 370/412
 Field of Search 370/229, 230,
370/232, 233, 234, 235, 395, 409, 412, 415, 416, 417, 418, 252, 253
 References Cited
U.S. PATENT DOCUMENTS
5,233,606 8/1993 Pashan et al 370/418
5,251,209 10/1993 lurkevich et al 370/468
5,278,828 1/1994 Chao 370/394
Prioritized subclasses ol cells within at least one quality ol service (QoS) level in an asynchronous transler mode (ATM) network element are described. Corresponding QoS queues are provided with one or more thresholds lor intelligent discard ol incoming cells within a QoS, based upon cell priority, at the onset ol queue congestion. Cells having a first priority within a QoS are discarded as a first queue threshold is achieved; cells having a higher priority are enqueued. A cell loss priority (CLP) bit is employed to provide a lurther degree ol cell discard prioritization. Dillerent traffic streams within a single queue have different priorities, enabling intelligent discard ol lower priority tralfic prior to complete queue congestion.
17 Claims, 2 Drawing Sheets
QUALITY OF SERVICE PRIORITY
FIELD OF THE INVENTION
The invention generally relates to the field of congestion 5 management in asychronous transfer mode (ATM) network elements, and specifically to prioritized cell subclasses within a respective quality of service level in an ATM network element.
BACKGROUND OF THE INVENTION
Within an asynchronous transfer mode (ATM) network element, such as a switch, cells are assigned to one of a number of quality of service (QoS) levels, each having associated delay and throughput characteristics, based upon 15 the connection definition for the respective cell. Such QoS levels include: constant bit rate (CBR); variable bit rate— real time (VBRO); variable bit rate —non-real time (VBR1); available bit rate (ABR); and unspecified bit rate (UBR). A cell is mapped to a queue based upon the respective QoS 20 definition as part of the process of reformatting the cell header and providing the cell to an appropriate output port or ports. During congestion, queues Can become full, leading to the indiscriminate discard of incoming cells.
A cell loss priority (CLP) bit associated with each cell provides some indication of whether a cell is more likely to be discarded. Initially set to zero, this bit may be reset according to network conditions and the policy of the network administrator, indicating that the associated cell is
subject to being discarded by the network. However, this bit is set in an environment where discarding of incoming cells takes place in a wholesale manner when a queue is completely congested.
SUMMARY OF THE INVENTION 35
Cells belonging to each of plural quality of service (QoS) levels are prioritized, resulting in the creation of priority subclasses within each QoS. Correspondingly, each QoS queue is provided with one or more thresholds or trip points 4Q for intelligent discard of incoming cells within the QoS, based upon the priority of the incoming cells, at the onset of congestion within the queue. As a first threshold is achieved, cells within the QoS having a lower priority are discarded, while cells having a higher priority are assigned to the ^ queue. In general, cells having a high priority are less likely to be discarded.
Each asynchronous transfer mode (ATM) connection is provided with a corresponding QoS and priority at switch configuration. As each cell is received within the switch, the 50 respective connection is identified and the predefined QoS and resulting priority are assigned for use within the switch according to the present invention.
Further refinement of prioritization within a cell of a particular QoS is provided through the use of the cell loss 55 priority (CLP) bit. A cell of a particular priority may be conditionally discardable, depending upon the value of the associated CLP bit.
Thus, different traffic streams within a single queue are allowed to have different priorities, enabling the intelligent 60 discard of lower priority traffic upon detection of increasing queue congestion, but before the respective queue is full.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of interconnected network 65 elements implementing prioritization within multiple QoS levels according to the present invention;
FIG. 2 is a table illustrating prioritization within a quality of service (QoS) queue according to the present invention; and
FIG. 3 is a table illustrating a first embodiment of the prioritization of FIGS. 1 and 2.
Cells received within an asynchronous transfer mode (ATM) network element, such as a switch, are provided with an internal header format based upon the connection defined for each incoming cell. With respect to FIG. 1, this internal header, for use in determining how each cell is to be directed through the switch and ultimately back into the ATM network, is provided by a look-up table 12 addressed by a VPI/VCI (virtual path identifier/virtual circuit identifier) pair in the received cell. Such may be accomplished through any manner known in the art or as disclosed in an application titled "ATM Address Translation Method and Apparatus" of the present assignee, filed May 26, 1996application Ser. No. 08/639,228. The internal header provides an indication of the quality of service (QoS) assigned to the respective connection of the received cell. Together, the internal header and the payload of the incoming cell form an intermediate form of the cell, which is routed through a switching fabric 18 according to the connection defined within the internal header, then mapped to a QoS queue 20, 22, 24, 26 based upon the respective QoS definition from the internal header.
In FIG. 1, a processing element 14 and associated memory 16 provide the intelligence required for analyzing the intermediate cell form and for directing the cell to the appropriate QoS queue 20, 22, 24, 26 after the cell has migrated through the switching fabric 18. In an exemplary embodiment of the present invention, the intelligence of the processing element 14 and associated memory 16 are embodied in a field programmable gate array (FPGA). Attached hereto as an Appendix is a Verilog module employed as a source for synthesizing the presently disclosed QoS subclass prioritization in such an FPGA.
The QoS field in the internal header is comprised of four bits. The upper two bits define to which of the four QoS levels the respective cell is assigned. The lower two bits are used to define one of four priorities assigned to the intermediate cell.
The memory 16 of the processing element 14, the FPGA in the exemplary embodiment, retains a table for each QoS queue 20, 22, 24, 26 correlating queue capacity with one or more thresholds or trip levels. The processing element 14 monitors the capacity of each queue 20, 22, 24, 26; as the unused capacity of each queue 20, 22, 24, 26 varies, the processing element 14 determines which of the one or more thresholds is currently achieved. At each threshold, cells of a first subclass of lower priorities are discarded, while cells of a second subclass of higher priorities are enqueued.
In FIG. 2, the foregoing table as implemented in the exemplary FPGA embodiment is illustrated. In particular, this table is for either of the two VBR QoS levels, variable bit rate—real time (qos=10xx) and variable bit rate—nonreal time (qos=llxx). This is reflected by the indicated value for the first two bits of qos at the top of each column in FIG. 2: "lx".
The second two bits in the four bit QoS field represent the priority level of the intermediate cell, as illustrated across the top of the columns in FIG. 2: PRIORITY 0 (qos=lx00); PRIORITY 1 (qos=lx01); PRIORITY 2 (qos=lxl0); and PRIORITY 3 (qos lxll). In the illustrated embodiment, PRIORITY 0 has the highest priority access to the respective