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MICROLOADING EFFECT CORRECTION
1. Field of the Invention 5 This invention relates to the field of semiconductor
devices. More particularly, the invention relates to a method and apparatus for correcting for microloading effects.
2. Description of the Related Art 10 One common step in modern approaches to integrated
circuit (IC) production is the use of an etching process after exposure of photoresist on the semiconductor to electromagnetic radiation (e.g. light).
There are number of different etching technologies and 15 methods available including, plasma etching and several types of ion beam etching. In some instances over etching, e.g. etching for an extended period of time compared to the normal etching period, has been used to reduce feature sizes. However, over etching worsens the microloading effect. 20
Of particular importance during etching processes is maintaining uniformity. Uniformity refers to evenness of etching for critical dimension, as well as uniformity of etching across a wafer and from wafer to wafer. At the microscopic level, etching rates and profiles depend on 25 features size and feature separation. Microscopic uniformity problems can be grouped into several categories including pattern-dependent etch effects, generally referred to as a microloading. More specifically, microloading refers to the dependence of the etch rate on feature separation for iden- 30 tically sized features and it results from the depletion of reactants when the wafer has a local, higher-density area.
From a terminology standpoint, critical dimension simply refers to the dimension (e.g. width) of a feature in the relevant direction. For example, a feature corresponding to a transistor can be conceived of as a one dimensional object on the mask since the length will change, but the critical dimension will not. Thus, for example if the transistors are being prepared with a target critical dimension of 1 fim, there can be multiple transistors with different lengths, e.g. some 5 fim, some shorter, some longer, but all might be designed to have critical dimension of 1 fim. (Note, a single mask may include similar features having different critical dimensions.)
Current optical proximity correction techniques are not well suited to accounting for microloading effects. Further, if existing approaches are used in a straightforward fashion they may be computationally infeasible with present day computer systems and hardware. 5Q
Accordingly, what is needed is a method and apparatus for correcting for microloading effects. Also suitable masks for producing integrated circuits that have been corrected for microloading effects. (As used herein, the term masks includes reticles.) 55
A method and apparatus for providing correction for microloading effects is described. Hybrid proximity correction techniques are used to make the problem computation- 60 ally more feasible. Specifically, if model based optical proximity correction techniques were used alone, the problem would be extremely complicated and further changes made to correct for optical errors would interact with changes made to correct microloading errors. 65
The approach groups feature edges in a layout into those edges, edges or edge segments, with a large edge separation
(group B), e.g. greater than n, and those having less than that separation (group A). More specifically, the straight line distance from neighboring edges to a given edge can be determined and edges, or edge segments, that are further than the given amount n placed into group B. The value of n is process technology dependent, for an example X=248 nm wavelength process, n=1.5 fim. Edges having a separation equal to n are placed into either group A or group B, in one embodiment they are placed in group B to be corrected for microloading effects.
The group B features are then corrected for microloading effects, or etch effects, using rules based correction. Rules based corrections can be applied extremely rapidly since there is minimal computational complexity as the layout is scanned for features, edges, and/or edge segments matching the rule criteria and then the rules are applied. For example, a rule might adjust an edge with a separation of 2.0 fim by 30 nm.
Next, both groups of edges, e.g. the entire layout portion being corrected, can be corrected using model based optical proximity correction (MOPC). The MOPC is applied using the output of the rule based correction as the ideal, or reference layout. Conceptually this can be viewed as the MOPC is trying to bring the layout so that after optical effects occur the pattern will be such that it is shaped as was computed is better (based on the rules) to account for the later occurring etch process.
In some embodiments, the ordering of the etch and optical effects are switched; however, such embodiments are likely to give less accurate corrections, but may still be useful. Approaches for developing appropriate etch and optical models are described as well. The models can be generated using measurements taken from test exposures. This ensures that the generated models are calibrated for the particular lithography process being used including the stepper, the resist, the etch, etc. In some embodiments, uncalibrated models are used based on assumed data or theoretical computations. This may be appropriate for testing purposes, if suitable test exposures cannot be obtained, and/or if only slight changes to the lithography process for a previously calibrated model are being made, etc.
BRIEF DESCRIPTION OF THE FIGURES
FIG. 1 is a process flow diagram for performing optical proximity correction (OPC) on a layout in a manner that corrects for microloading effects.
FIG. 2 is a layout for a portion of an integrated circuit.
FIG. 3 depicts rules based OPC correction of a portion of the layout of FIG. 2 for microloading effects.
FIG. 4 depicts the model based OPC range for the layout of FIG. 3 for use in performing optical proximity correction for optical and resist effects.
FIG. 5 is a process flow diagram for generating OPC rules based on a calibrated etching model.
FIG. 6 is a process flow diagram for generating a calibrated model for a given lithography process.
As noted, uniformity of critical dimension (CD) of features is an important aspect of etching processes. In order to maintain uniformity of CD, microloading effects should be considered. An approach to correcting for microloading effects to provide uniformity of critical dimension will be discussed first. Next, a more detailed setup of the parameters
and models used will be considered. Finally several alternative embodiments will be considered. Efficient Microloading Effect Correction
FIG. 1 is a process flow diagram for performing optical proximity correction (OPC) on a layout in a manner that 5 corrects for microloading effects. The process of FIG. 1 is best understood in conjunction with the respective processes described on FIGS. 5 and 6 and the example shown in FIGS. 2-4.
The process starts at step 130 when edge segments of 10 features from a layout 100 are divided into two groups (group A and group B) based on their separation from one another. Group A will be comprised of relatively densely packed edge segments (e.g. separations /an), while group B will be comprised of semi-isolated and isolated edge is segments (e.g. separations /an). (Note: Edge segments with a separations fim can be placed in either group A or group B. In one embodiment they are placed in group B to ensure correction for microloading effects.)
In this example, the separation used is 1.5 fim for a sample 20 X=248 nm process. More generally, the separation n should be larger than the range of optical proximity effects for the particular process and based on the observed range of microloading/etch effects for the process.
Different edges, and even portions of a single edge, of a 25 feature in a layout may have different characteristics visa-vis their relative isolation from other features. FIG. 2 shows an exemplary layout 200 including a number of features. The grouping of edges for the feature 220 in the layout 200 will be considered. One approach is to measure 30 the line from the corner of other layout objects toward edges of the feature 220 (the measurement line should be perpendicular to the orientation of the edge). Six measurement lines are shown as dashed lines with arrowheads. The edge to edge measure 230 shows the distance between the top corner 35 of a nearby feature and one point on the right edge of feature 220. Further down the edge 220 another edge to edge measure 232 intersects the right edge of the feature 220. Still further down, the edge to edge measures 232, 234 and 236 intersect the feature 220 along the right edge. Note however, 40 that the region 210 between the edge to edge measure 232 and the edge to edge measure 236 is actually >n fim (here, n=1.5 fim) from other edges. Thus the region 210 of the right edge of the feature 220 will fall into group B. The distance between the left edge of the feature 220 and nearby features 45 is shown by edge to edge measures 238 and 240. In contrast, the other portions of the side edges of the feature 220 are <1.5 fim from nearby edges and would fall into group A. The grouping can be done in parallel or series for the other layout features being corrected for microloading effects and optical 50 proximity effects.
After grouping, the process continues at step 140 with rule based OPC being applied to account for etch effects on group B edges. The OPC etch rules 110 can be used as the rules to modify the group B (separations fim) edge seg- 55 ments. The generation of the OPC etch rules 110 will be discussed in greater detail in relation to the process of FIG. 5, below. Turning to the example layout of FIG. 2, the region 210 is in group B and should be corrected for etch effects. Here, FIG. 3 shows a layout 300 that corresponds to the 60 layout 200 after rules based correction of step 140 has been applied for the feature 220. The rule correction 310 caused the width of the feature in the region 210 to be made smaller (e.g. downward biased, narrowed, reduced in width, etc.) to account for the microloading effect. This correction reduces 65 the width of the feature 320 in that region because semiisolated and isolated edge segments are likely to etch more
slowly and thus be too large in size. (Note: The downward bias is exaggerated for illustrative purposes in FIG. 3. For example, the downward bias might be 30 nm for a 150 nm target critical dimension. The specific bias will have to be determined for each process technology and model.)
Next, at step 150, model based OPC is applied to model the resist and optical effects on all edge segments, e.g. both group A and group B. A calibrated optical model 120 can be used to describe those effects and the final OPC layout 160 can be generated. The generation of such an optical model is described in greater detail with reference to FIG. 6.
In some embodiments, the model based OPC uses the modified shapes generated at step 140 as the ideal (or target) shape. Thus returning to performing this process on the layout 200, at step 150, the ideal shape for the feature 220 will be the shape of the feature 320 generated at step 140 during correction for microloading effects.
FIG. 4 depicts the model based OPC range for the layout of FIG. 3 for use in performing optical proximity correction for optical and resist effects. Here, the layout 400 includes the feature 320, the ideal shape that model OPC will attempt to correct the layout to generate. An evaluation point 410 on the ideal layout is shown with an "X". A dashed line shows the OPC range 420, which is a circle of radius R from the evaluation point 410.
After the model based OPC is applied at step 150, the OPC layout 160 can be output (not shown). In some circumstances, there may be additional or intermediate steps added to the process of FIG. 1 to permit viewing, simulation, and/or testing of the intermediate and final output layouts.
In one embodiment, the process of FIG. 1 is added to an OPC software package such as the Photolynx(TM) software from Transcription Enterprises, a Numerical Technologies Company, from San Jose, Calif. Etch Model and Rule Generation
FIG. 5 is a process flow diagram for generating OPC rules based on a calibrated etching model. This process can be used to generate the OPC etch rules 110 for use at step 140 of the process of FIG. 1. The generated rules will provide rule-based OPC correction for certain types of microloading effects.
The process starts with a test pattern 500. The test pattern is characterized by a number of line segments of differing widths at different separations. For example, the test pattern might include features with a critical dimension of 1 fim spaced at varying densities, e.g. minimum design pitch up through 10 fim. This could be repeated for each different critical dimension size being used in a particular layout and perhaps at differing orientations, e.g. some placed horizontally and other vertically. At step 510, a test mask is fabricated according to the test pattern.
Then, at step 520, a wafer is exposed using the test mask and the resist on the wafe developed, step 530. Next, at step 540, the critical dimension (CD) of features in the resist are measured, and stored as resist CD measurements 545. The resist CD measurements 545 can be used to calibrate optical models, for more information on that see below.
According to one embodiment, only resist CD measurements for separations less than a predetermined distance n, e.g. <1.5 fim, are stored in the resist CD measurements while only the resist CD measurements for separations greater than (or equal to) the predetermined distance are used for the remaining steps of the process of FIG. 5. For the remainder of the discussion of FIG. 5 and FIG. 6 it will be assumed that this "grouping" of resist CD measurements has occurred and that the resist CD measurement 545 contains only the measurements for separations less than the predetermined