(56) References Cited
U.S. PATENT DOCUMENTS
6,158,022 A 12/2000 Avidan
6,581,197 B1 6/2003 Foutz et al.
6,604,227 B1 8/2003 Foltin et al.
6,609,233 B1 8/2003 Foltin et al.
6,925,623 B2 * 8/2005 Roethig ...................... .. 716/115
6,996,515 B1 2/2006 Foltin et al.
7,036,100 B2 4/2006 Tyler et al.
7,454,719 B2 * 11/2008 Roethig ...................... .. 716/113
7,464,349 B1 * 12/2008 Keller et al. ..... .. 716/136
7,594,209 B2 * 9/2009 Abbaspour et al. 716/108
7,788,617 B2 * 8/2010 Bhanji et al. ..... .. 716/113 2005/0060674 A1* 3/2005 Roethig .... .. 716/5 2005/0268262 A1* 12/2005 Roethig .. 716/5 2007/0143723 A1* 6/2007 Kawakami .. 716/6 2008/0243414 A1* 10/2008 Oh et al. .......... .. .. 702/85 2008/0270960 A1* 10/2008 Abbaspour et al. 716/6 2009/0228850 A1* 9/2009 Bhanji et al. .................... .. 716/6
A method for converting interconnect parasitics of an interconnect netWork into sleW dependent pin capacitances utilizes charge matching betWeen predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as sleW dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts.
