Tileable field-programmable gate array architecture

(21) Appl. No.: 10/066,398

(22) Filed: Jan. 30, 2002

Related U.S. Application Data

(63) Continuation-in-part of application No. 09/654,240, filed on Sep. 2, 2000, now Pat. No. 6,476,636.

(51) Int. CI.7 H03K 19/177

(52) U.S. CI 326/41; 326/38; 326/39;

716/12; 716/14

(58) Field of Search 326/38-41; 716/12,

716/14

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FOREIGN PATENT DOCUMENTS

EP 0 415 542 A2 3/1991 H03K/19/173

* cited by examiner
Primary Examiner—-Vibol Tan

(74) Attorney, Agent, or Firm—Sierra Patent Group, Ltd. (57) ABSTRACT

An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.

10 Claims, 26 Drawing Sheets

GG[0.2.4.S] . A . 226

FPGA Tile 20

FPGATile 20

FPGA 22

FIG. 2