Sequential flow-control and FIFO memory devices having error detection and ...

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SEQUENTIAL FLOW-CONTROL AND FIFO
MEMORY DEVICES HAVING ERROR

DETECTION AND CORRECTION
CAPABILITY WITH DIAGNOSTIC BIT

GENERATION 5

CROSS-REFERENCE TO RELATED
APPLICATIONS

This application is related to U.S. application Ser. No. 10 10/612,849, filed Jul. 3, 2003; Ser. No. 10/613,246, filed Jul. 3, 2003; Ser. No. 10/639,163, filed Aug. 11, 2003; and Ser. No. 10/721,974, filed Nov. 24, 2003, the disclosures of which are hereby incorporated herein by reference.

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FIELD OF THE INVENTION

The present invention relates to integrated circuit memory devices and methods of operating same, and more particularly to buffer memory devices and methods of operating 20 buffer memory devices.

BACKGROUND OF THE INVENTION

Semiconductor memory devices can typically be classi- 25 fied on the basis of memory functionality, data access patterns and the nature of the data storage mechanism. For example, distinctions are typically made between read-only memory (ROM) devices and read-write memory (RWM) devices. The RWM devices typically have the advantage of 30 offering both read and write functionality with comparable data access times. Typically, in RWM devices, data is stored either in flip-flops for "static" memory devices or as preset levels of charge on a capacitor in "dynamic" memory devices. As will be understood by those skilled in the art, 35 static memory devices retain their data as long as a supply of power is maintained, however, dynamic memory devices require periodic data refreshing to compensate for potential charge leakage. Because RWM devices use active circuitry to store data, they belong to a class of memory devices 40 known as "volatile" memory devices because data stored therein will be lost upon termination of the power supply. ROM devices, on the other hand, may encode data into circuit topology (e.g., by blowing fuses, removing diodes, etc.). Since this latter type of data storage may be hardwired, 45 the data cannot be modified, but can only be read. ROM devices typically belong to a class of memory devices known as "nonvolatile" memory devices because data stored therein will typically not be lost upon termination of the power supply. Other types of memory devices that have been 50 more recently developed are typically referred to as nonvolatile read-write (NVRWM) memory devices. These types of memory devices include EPROM (erasable programmable read-only memory), E2PROM (electrically erasable programmable read-only memory), and flash memories, for 55 example.

An additional memory classification is typically based on the order in which data can be accessed. Here, most memory devices belong to the random-access class, which means that memory locations can be read from or written to in random 60 order, typically by supplying a read or write address. Notwithstanding the fact that most memory devices provide random-access, typically only random-access RWM memories use the acronym RAM. Alternatively, memory devices may restrict the order of data access to achieve shorter data 65 access times, reduce layout area and/or provide specialized functionality. Examples of such specialized memory devices

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include buffer memory devices such as first-in first-out (FIFO) memory devices, last-in first-out (LIFO or "stack") memory devices, shift registers and content addressable memory (CAM) devices.

A final classification of semiconductor memories is based on the number of input and output ports associated with the memory cells therein. For example, although most memory devices have unit cells therein that provide only a single port which is shared to provide an input and output path for the transfer of data, memory devices with higher bandwidth requirements often have cells therein with multiple input and output ports. However, the addition of ports to individual memory cells typically increases the complexity and layout area requirements for these higher bandwidth memory devices.

Single-port memory devices are typically made using static RAM cells if fast data access times are requiring, and dynamic RAM cells if low cost is a primary requirement. Many FIFO memory devices use dual-port RAM-based designs with self-incrementing internal read and write pointers to achieve fast fall-through capability. As will be understood by those skilled in the art, fall-through capability is typically measured as the time elapsing between the end of a write cycle into a previously empty FIFO and the time an operation to read that data may begin. Exemplary FIFO memory devices are more fully described and illustrated at section 2.2.7 of a textbook by A. K. Sharma entitled "Semiconductor Memories: Technology, Testing and Reliability", IEEE Press (1997).

In particular, dual-port SRAM-based FIFOs typically utilize separate read and write pointers to advantageously allow read and write operations to occur independently of each other and achieve fast fall-through capability since data written into a dual-port SRAM FIFO can be immediately accessed for reading. Since these read and write operations may occur independently, independent read and write clocks having different frequencies may be provided to enable the FIFO to act as a buffer between peripheral devices operating at different rates. Unfortunately, a major disadvantage of typical dual-port SRAM-based FIFOs is the relatively large unit cell size for each dual-port SRAM cell therein. Thus, for a given semiconductor chip size, dual-port buffer memory devices typically provide less memory capacity relative to single-port buffer memory devices. For example, using a standard DRAM cell as a reference unit cell consuming one (1) unit of area, a single-port SRAM unit cell typically may consume four (4) units of area and a dual-port SRAM unit cell typically may consume sixteen (16) units of area. Moreover, the relatively large unit cells of a dual-port SRAM FIFO may limit the degree to which the number of write operations can exceed the number of read operations, that is, limit the capacity of the FIFO.

To address these limitations of dual-port buffer memory devices, single-port buffer memory devices have been developed to, among other things, achieve higher data capacities for a given semiconductor chip size. For example, U.S. Pat. No. 5,546,347 to Ko et al. entitled "Interleaving Architecture And Method For A High Density FIFO", assigned to the present assignee, discloses a memory device which has high capacity and uses relatively small single-port memory cells. However, the use of only single port memory cells typically precludes simultaneous read and write access to data in the same memory cell, which means that single-port buffer memory devices typically have slower fall-through time than comparable dual-port memory devices. Moreover, single-port buffer memory devices may use complicated