United States Patent  [li] Patent Number: 5,386,131
Sato  Date of Patent: Jan. 31,1995
 SEMICONDUCTOR MEMORY DEVICE
 Inventor: Natsuki Sato, Tokyo, Japan
 Assignee: NEC Corporation, Tokyo, Japan
 Appl. No.: 944,241
 Filed: Sep. 14,1992
 Foreign Application Priority Data
Sep. 13, 1991 [JP] Japan 3-262839
 Int. Cl.« H01L 29/68; H01L 29/78;
 U.S. CI 257/301; 257/296;
257/300; 257/303; 257/305; 257/306
 Field of Search 257/296, 300, 301, 303,
 References Cited
U.S. PATENT DOCUMENTS
4,752,819 6/1988 Koyama 357/41
4,803,535 2/1989 Taguchi 257/301
4,920,390 4/1990 Fuse et al 257/301
4,922,313 5/1990 Tsuchiya 357/23.6
5,027,172 6/1991 Jeon 257/303
5,065,215 11/1991 Kubota 357/45
5,066,609 11/1991 Yamamoto et al 437/52
5,111,259 5/1992 Teng et al 357/23.6
5,136,533 8/1992 Harari 365/149
FOREIGN PATENT DOCUMENTS
59- 191373 10/1984 Japan .
60- 126861 7/1985 Japan .
4-65872 3/1992 Japan .
Primary Examiner—Sara W. Crane
Assistant Examiner—Valencia M. Wallace
Attorney, Agent, or Firm—Burns, Doane, Swecker &
A DRAM having memory cells each consisting of a MOS transistor and a trench-stack capacitor built at a p-type silicon substrate. The MOS transistor comprises a source region made of the first diffused n- layer, and a drain region composed of the first diffused n- layer and the first diffused n+ layer self-aligned with respect to a bit contact hole. At the surface of the p-type silicon substrate is formed a trench penetrating through the source region near the gate electrode of the MOS transistor working also as a word line. The capacitor is built to extend deep into a U-shaped section. The second diffused n_ layer is formed at the the trench sidewall surface of the p-type silicon substrate, and the second insulating film is formed over the sidewall of the trench. The second diffused n+ layer is formed at the trench bottom surface of the p-type silicon substrate. The bottom face of the trench functions as a node contact hole of the memory cell. The storage node electrode of the trench-stacked capacitor is electrically connected through the node contact hole, the second diffused n+ layer and the second diffused n- layer to the source region. The structure mentioned above has not only the same effects as the conventional trench-stacked capacitor DRAM over the trench capacitor DRAM but also an effect of less memory cell space than the conventional trench-stacked capacitor DRAM.
3 Claims, 7 Drawing Sheets