Subsurface zener diode and method of making

[54] SUBSURFACE ZENER DIODE AND METHOD OF MAKING

[75] Inventors: Stephen R. Burnham; William J.

Lillis, both of Tucson, Ariz.

[73] Assignee: Burr-Brown Corporation, Tucson, Ariz.

[21] Appl. No.: 859,454
[22] Filed: May 5, 1986

[51] Int. CI." H01L 29/90

[52] U.S. CI 357/13; 357/88;

357/90; 357/52

[58] Field of Search 357/13, 88, 90, 52

[56] References Cited

U.S. PATENT DOCUMENTS

3,881,179 4/1975 Howard, Jr 357/13

4,127,859 11/1978 Nelson 357/13

4,136,349 1/1979 Tsang 357/13

4,213,806 7/1980 Tsang 148/187

FOREIGN PATENT DOCUMENTS

0082331 6/1983 European Pat. Off. 357/13 Z

2257823 6/1974 Fed. Rep. of Germany .

2130792 6/1984 United Kingdom 357/13

OTHER PUBLICATIONS

"The Theory and Practice of Microelectronics", Ghandhi, 1968, p. 390, Wiley & Sons, N.Y.

"On-Chip Heater Helps to Stabilize Monolithic Reference Zener", Dobkin, Electronics, 9/16/76, pp. 106-112.

Primary Examiner—Andrew J. James

Assistant Examiner—Jerome Jackson

Attorney, Agent, or Firm—Cahill, Sutton & Thomas

[57] ABSTRACT

A subsurface zener diode is formed in an N_ epitaxial region formed on a P type substrate. The N~ epitaxial region is isolated by a P+ isolation region. An N+ buried layer region is disposed between a portion of the N~ epitaxial region and the P type substrate. A first P+ region is formed in the middle of the N- epitaxial region at the same time as the P+ isolation regions. Second and third adjacent P+ regions also are formed in the N~ epitaxial region adjacent to and slightly overlapping the first P+ region, all three P+ regions terminating at the N+ buried layer. An N+ region, formed during an emitter diffusion operation, has first and second opposed edges centered within the overlapping portions of the first, second, and third P+ regions. Two other opposed edges of the N+ region extend beyond the other edges of the first P+ region, forming N+N~ contacts to the N~ epitaxial region, enabling it to be reverse biased without an additional N+ contact region and a corresponding metal conductor. Masking alignment tolerances in the direction of the N+N~ overlap are eased, increasing overall processing yields.

8 Claims, 9 Drawing Figures