METHOD AND APPARATUS FOR POWER MANAGEMENT OF AN INTEGRATED CIRCUIT
 Inventors: Keng L. Wong, Portland; Kelly J.
Fitzpatrick, Beaverton; Jeffrey E.
Smith, Aloha, all of Qreg.
 Assignee: Intel Corporation, Santa Clara, Calif.
 Appl. No.: 597,363
 Filed: Feb. 8,1996
Related U.S. Application Data
 Division of Sec. No. 86,044, Jim. 30, 1993, Pat. No. 5,586, 307.
 Int Cl.fi G06F 1/10; G06F 1/32
 U.S. CI 395/560; 395/750
 Field of Search 395/560, 750
 References Cited
U.S. PATENT DOCUMENTS
5,167,024 11/1992 Smith etal 395/750
5,172,330 12/1992 Watanabe et al 364/491
5,398,262 3/1995 Ahuja 375/356
5,428,790 6/1995 Harper etal 395/750
5,446,410 8/1995 Nakakura 327/565
5,546,591 8/1996 Wvuzburg et al 395/750
5,560,024 9/1996 Harper etal 395/750
5,586,332 12/1996 Jain etal 395/750
5,603,036 2/1997 Wells etal 395/750
FOREIGN PATENT DOCUMENTS
0359177 3/1990 European Pat. Off. .
2236415 9/1989 United Kingdom .
Primary Examiner—Thomas M. Heckler
Attorney, Agent, or Firm—Blakely, Sokoloflf, Taylor &
A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry. The present invention additionally offers the capability of selectively powering down various components within the integrated device with a power management unit and enable network that is included as a component of the clock distribution system
13 Claims, 11 Drawing Sheets