SEMICONDUCTOR MEMORY
 Inventor: Masaharu Wada, Yokohama, Japan
 Assignee: Kabushiki Kaisha Toshiba, Kawasaki, Japan
 Appl. No.: 09/181,976
 Filed: Oct. 29, 1998
 Foreign Application Priority Data
Oct. 30, 1997 [JP] Japan 9-298046
 Int. CI. G11C 7/00
 U.S. CI 365/200; 365/230.03
 Field of Search 365/200, 230.03,
 References Cited
U.S. PATENT DOCUMENTS
5,475,648 12/1995 Fujiwara 365/200
Fujii, et al. "A Low-Power Sub 100 ns 256K Bit Dynamic RAM," IEEE Journal ol Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983, pp. 441-445.
A memory cell array is composed ol N (l = N=Nmax) blocks. A redundancy memory is always composed ol Nmax blocks. A block decoder selects one ol the N blocks ol the memory cell array based on a block address signal. A redundancy memory decoder selects one ol the Nmax blocks ol the redundancy memory based on a redundancy memory selection address signal. When the number ol blocks ol the memory cell array and the number ol blocks ol the redundancy memory are different from each other, the N blocks ol the memory cell array are in a one to one correspondence with N blocks ol the Nmax blocks ol the redundancy memory and the redundancy memory decoder selects one ol the N blocks ol the redundancy memory. The other blocks than the N blocks ol the redundancy memory are left unused.
6 Claims, 30 Drawing Sheets