Multiplexed memory timing with block reset and secondary memory

United States Patent [19]

Urbanus

[54] MULTIPLEXED MEMORY TIMING WITH

BLOCK RESET AND SECONDARY MEMORY

[75] Inventor: Paul M. Urbanus, Dallas, Tex.

[73] Assignee: Texas Instruments Incorporated,

Dallas, Tex.

[21] Appl. No.: 264,387
[22] Filed: Jun. 23,1994

[51] Int. CI.6 H04N 5/74

[52] U.S. CI 348/771; 348/718; 348/759;

345/84

[58] Field of Search 348/571, 718,

348/761, 762, 764, 759, 766, 771; 345/84, 85, 86; H04N 5/74

[56] References Cited

U.S. PATENT DOCUMENTS

4,039,890 8/1977 Bailey et al 345/82

4,495,492 1/1985 Anderson et al 345/86

4,638,309 1/1987 Ott 345/84

5,278,652 1/1994 Urbanus et al 348/571

5,339,116 8/1994 Urbanus et al 348/771

HIM

US005499062A

[li] Patent Number: 5,499,062

[45] Date of Patent: Mar. 12,1996

Primary Examiner—James J. Groody

Assistant Examiner—Jeffrey S. Murrell

Attorney, Agent, or Firm—Julie L. Reed; James C. Kester

son; Richard L. Donaldson

[57] ABSTRACT

A spatial light modulator array with adaptable multiplexed memory architecture. The modulator has an array of individually controllable pixels, where a predetermined number of pixels are assigned to a memory cell (16). The memory cell receives data from an input bus (14). On a signal (22), the memory cell transfers its data to a secondary memory (18), and to the activation circuitry (20) of one of its assigned pixels. On a second signal, the pixel responds to the data on the activation circuitry. When the display time of the data is less than the load time for the memory cell, the secondary memory is set with a second signal (24) so as to make the pixel dark and another control signal makes the pixels respond to the memory. In this way, the load time is lengthened and the data rate remains relatively low, even though the number of bits of intensity may not be the same as the number of bits of intensity used to determine the number of pixels assigned to each memory cell.

7 Claims, 2 Drawing Sheets

Mar. 12, 1996

Sheet 2 of 2 5,499,062

FIG. 3A

DATA INPUT BUS

SHADOW
TRANSFER

ELECTRODE
STATE

PIXEL
TRANSFER

PIXEL DATA
STATE

SHADOW SET/CLEAR

1

MULTIPLEXED MEMORY TIMING WITH BLOCK RESET AND SECONDARY MEMORY

BACKGROUND OF THE INVENTION

1. Field of the Invention 5 This invention relates to spatial light modulators, more

particularly to memory schemes supporting spatial light modulator arrays.

2. Background of the Invention

10

In one form, spatial light modulators consists of an array of individually addressable elements, such as liquid crystal display panels or digital rnicromirror devices. These examples of modulator arrays have many uses, such as printers, displays, and optical processing. This discussion 5 will focus on display systems.

In some applications, these arrays function in binary mode, where each individual element receives either an ON or an OFF signal. Typically, the elements, or pixels, of the array that receive the ON signal form the image the viewer 20 receives, either directly, from a screen or through optics.

To individually address each pixel, each modulator array must have circuitry allowing signals to reach each pixel and activate it to respond in a certain way. One approach requires one memory cell per pixel, where the memory cell receives 25 the information for the pixel's next state. This information results from the scheme used to produce the displayed images.

One technique for production of images, called pulse width modulation, has each pixel turn ON and OFF repeat- 30 edly within a video frame time. This method controls the intensity of a given pixel by how many times within the frame the pixel is ON, or transmitting light to the final image. Digitally, gray levels are achieved by using weighted bits of data. 35

For example, to achieve 16 gray levels, each pixel receives 4 bits of data over the time period of one frame. The frame time is divided into 15 slices, 1-15. The most significant bit (MSB) would then receive 8 of those time slices for it to display its data. The next most significant bit would 40 receive 4, etc. Techniques exist that allow these time slice to be assigned to the bits of data in non-contiguous sections. For example, the MSB may be displayed for 2 time slices at once, then be displayed for the other 6 time slices at another time, or even be divided up again. A detailed description of 45 this method using the DMD as an example is in U.S. Pat. No. 5,278,652, "DMD Architecture and Timing for Use in a Pulse-Width Modulated Display System."

The above technique requires memory for keeping the 5Q data to be displayed and sending it to the pixel at the appropriate time. One technique uses one memory cell per pixel. The cell receives the pixel's data, the pixel gets a control signal allowing it to react to the new data is latched into its new state. Meanwhile, the cell is receiving the data 5S for the pixel's next state. When the pixel transfer signal occurs, the pixel reacts to its new data.

The above described method focuses on an entire array receiving the pixel transfer signal at once. However, techniques exist that allow any one pixel to receive the transfer 6o signal by itself. This allows for a much lower data rate making the system much more manageable. One such method is discussed in U.S. patent application Ser. No. 08/002,627, "Pixel Control Circuitry for Spatial Light Modulator." 65

This particular technique, often referred to as split reset, uses less than one memory cell per pixel, with tile number

2

of pixels per memory cell called "fanout." This architecture will be referred to more accurately as a multiplexed memory architecture. The memory cell receives the data for a set of pixels, rather than just one. To have the peak data rate most closely match the average data rate, the fanout is calculated as:

2n-1

FANOUTmllx = - — ,

n

where n=the number of bits of intensity. Therefore, if 4 bits of intensity were desired, there would be a fan out of 24-l, or 15, divided by 4, equalling 3.75 pixels. Since fractional pixels are impossible, there would be 4 pixels per memory cell.

One problem with the above approach is that the number of levels of intensity is linked to the number of pixels per memory cell. The number of pixels per memory cell must be determined before the device is fabricated. Using a device with a set fanout for a different number of bits of intensity increases the data rate, which eliminates the main advantage of using multiplexed memory architecture.

Therefore, if the number of levels of intensity is different, different devices need to be fabricated to keep system costs down. A need exists for a method that makes the multiplexed memory architecture scheme more flexible and eliminates the need for specially fabricated devices.

SUMMARY OF THE INVENTION

An aspect of the invention is a spatial light modulator with an array of individually addressable pixels. Each pixel may be set and reset in response to a signal delivered to the pixel. A pixel consists of an active area, whether reflective or transmissive, and activation circuitry. The signals are passed to the pixels via a memory cell, with more than one pixel receiving from any one memory cell. The number of pixels in connection with a memory cell is decided before device fabrication, depending upon the number of bits of intensity.

One aspect of the invention allows a device fabricated with a set number of pixels per memory cell to be used for several applications while minimizing the increase in the peak data rate. The same device could be used for two systems where each system uses a different number of bits of intensity, regardless of the fixed fanout of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and for further advantages thereof, reference is now made to the following Detailed Description taken in conjunction with the accompanying Drawings in which:

FIG. 1 shows a block diagram example of a multiplexed memory architecture memory cell and its assigned pixel elements.

FIG. 2 shows a block diagram example of a multiplexed memory architecture memory cell with a shadow cell and its assigned pixel elements.

FIGS. 3a-3c shows the timing diagram for a multiplexed memory architecture memory cell with a shadow cell and its assigned pixel elements.

DETAILED DESCRIPTION OF THE
PREFERRED EMBODIMENTS

Binary spatial light modulators are modulators with arrays of individually addressable pixels which have either an ON or OFF state. Examples are liquid crystal displays (LCD),