(i9) United States
(12) Patent Application Publication
Becker et al.
(54) CELL OF SEMICONDUCTOR DEVICE
HAVING SUB-193 NANOMETERS-SIZED
GATE ELECTRODE CONDUCTIVE
STRUCTURES FORMED FROM
RECTANGULAR SHAPED GATE
ELECTRODE LAYOUT FEATURES DEFINED
ALONG AT LEAST FOUR GATE ELECTRODE
(75) Inventors: Scott T. Becker, San Jose, CA
(US); Michael C. Smayling, San
Jose, CA (US)
MARTINE PENILLA & GENCARELLA, LLP 710 LAKEWAY DRIVE, SUITE 200 SUNNYVALE, CA 94085 (US)
(73) Assignee: Tela Innovations, Inc., Campbell, CA(US)
(21) Appl.No.: 12/571,357
(22) Filed: Sep. 30, 2009
Related U.S. Application Data
(63) Continuation of application No. 12/212,562, filed on Sep. 17, 2008, which is a continuation of application No. 11/683,402, filed on Mar. 7, 2007, now Pat. No. 7,446,352.
(60) Provisional application No. 60/781,288, filed on Mar. 9, 2006.
(51) Int. CI.
H01L 27/088 (2006.01)
(52) U.S. CI 257/208; 257/E27.06
A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width size of the conductive features within a five wavelength photolithographic interaction radius within the gate electrode level is less than a wavelength of light of 193 nanometers. The cell also includes a number of interconnect levels formed above the gate electrode level.